MONARCH-E OVERVIEW
The Monarch-E Frame Synchronizer / Telemetry Simulator with Reed-Solomon Encoder/Decoder is a PCI-based serial I/O board that supports both CCSDS (for Conventional and Advanced Orbiting Systems) and time-division multiplexed (TDM) telemetry and command formats. The board's integrated Reed-Solomon Encoder and Decoder provide complete block error detection and correction for each of the CCSDS-recommended grades of service for Advanced Orbiting Systems.

SERIAL INPUT CHANNEL
The Monarch-E Serial Input Channel accepts serial clock and data, then outputs processed frame data to the PCI Bus. The input channel performs frame synchronization, derandomization, deinterleaving, Reed-Solomon error detection and correction, CRC error detection, time tagging, and quality annotation.  For CCSDS telemetry, the serial input logic synchronizes to channel access data units and formats them for input to the Reed-Solomon (RS) Decoder, while for TDM telemetry, the serial input logic bypasses the RS Decoder and outputs frame data directly to the PCI interface.

SERIAL OUTPUT CHANNEL
The Monarch-E Serial Output Channel performs parallel-to-serial conversion, CRC encoding, pseudo-randomization, and convolutional encoding at up to 25 Mbps. It contains a programmable frequency synthesizer with an output range from 100 Hz to 25 MHz, with 0.1 Hz resolution.

REED-SOLOMON ERROR CORRECTION (RSEC)
The Monarch-E Reed-Solomon Error Correction chip accepts parallel data from the board's Serial Input Logic. It performs RS (255,223) VCDU error correction with interleaving depth from 1 to 8, RS (10,6) VCDU header error correction, and real-time quality generation and annotation. Shortened code blocks are also supported. The RSEC chip outputs corrected VCDUs with quality annotation to the PCI interface.

REED-SOLOMON ENCODER
The board's Reed-Solomon Encoder is implemented in a Field Programmable Gate Array. The Encoder accepts parallel data from the PCI interface and performs RS (255,223) VCDU encoding with an interleave depth from 1 to 8. Shortened code blocks are also supported. The R/S Encoder outputs interleaved code words to the Serial Output Channel.

Serial Input/Output Options

• Data rates to 25 Mbps
• TTL signals: 50-Ohm termination, BNC connectors
• RS-422 signals: 124-Ohm termination (62 Ohm to ground on each signal), TRIAX connectors

Frame Synchronizer

• Programmable frame sync pattern up to 32 bits
• Programmable frame sync mask up to 32 bits
• Programmable sync pattern error threshold up to 15 bit errors
• Adaptive sync strategy with 0 to 7 check frames and 0 to 7 flywheel frames
• Programmable bit slip window from 0 to + 3
• Auto-polarity detection and correction
• Frame length up to 8192 words/frame
• Programmable word size from 4 to 16 bits

De-Randomizer

• Exclusive OR received frame data following sync pattern with pseudo-random pattern given by  h(x) = x^8 + x ^7 + x^5 + x^3 + 1
• Shift register is initialized to all "ones" at the start of each frame
• Reed-Solomon Error Correction
• CCSDS Reed-Solomon (255,223) error correction
• Support for shortened code blocks using "virtual" fill
• Interleave depth from 1 to 8
• CCSDS Reed-Solomon (10,6) header error correction
• Real-time quality generation and annotation for each VCDU

CRC Frame Error Control

• Computes frame error control field using the polynomial g(x) = x^16 + x^12 + x^5 + 1
• Feedback shift register is initialized to all "ones" at the start of each frame
• Overlay computed CRC remainder into output frame
• Programmable inclusion/exclusion of Attached Sync Marker

PCI Interface

• Based on PLX 9080
• 133 MBps data transfer rate
• Support for "Plug and Play" auto-configuration

Telemetry Simulator

• Programmable clock and data polarity
• Frame length up to 8192 words/ frame
• Programmable word size from 4 to 16 bits
• Programmable output frequency from 100 Hz to 25 MHz with 0.1 Hz resolution

Reed-Solomon Encoding

• CCSDS Reed-Solomon (255,223) encoding
• Support for shortened code blocks using "virtual" fill
• Interleave depth from 1 to 8

Pseudo-Randomizer

• Exclusive OR frame data following sync pattern with pseudorandom pattern given by h(x) = x^8 + x^7 + x^5 + x^3 + 1
• Shift register is initialized to all "ones" at the start of each frame

Convolutional Encoder

• Rate 1/2, constraint-length 7, convolutional code
• Connection vectors G1 =1111001 and G2 = 1011011
• Programmable parity order and parity inversion