PCI-6800-BV OVERVIEW
The PCI-6800-BV is a high-performance combined bit synchronizer and Viterbi decoder for the PCI bus. The board accepts single-ended or differential data and outputs the recovered data and clock signal for further processing by the host system. Its state-of-the-art design provides bit error performance within 1 dB of theory.

FUNCTIONAL DESCRIPTION
Signals entering the PCI-6800-BV are routed to the board's Digital Costas Loop (DCL). The DCL performs baseband processing tasks including matched filtering, carrier tracking, bit synchronization, and soft-decision slicing. In addition, it provides second order loop filters for carrier tracking and symbol timing recovery. The DCL outputs 3-bit soft symbols and clock to the Viterbi Decoder, and also provides hard-decision bit data and clock output.

VITERBI DECODER
The PCI-6800-BV's onboard Viterbi decoder supports the CCSDS and INTELSAT standard Rate ½, Constraint Length 7 convolutional code. It accepts 3-bit soft symbols at rates up to 10 million symbols per second, outputting recovered bit data and clock. The Viterbi decoder also offers built-in synchronization and bit error rate monitoring circuits.

PCI INTERFACE
The board's PCI Interface is based on the PLX 9050. It provides access to the PCI-6800-BV's control and status registers via the host computer's PCI bus.

INCLUDED SOFTWARE
Avtec provides an intuitive Windows application that can be used to configure the PCI-6800, as well as monitor the board's status and performance. A Windows driver and DLL are available to users wishing to develop their own applications, as well as a LabVIEW VI library.

Inputs

• Two input sources (software-selectable)
• 0.1 V to 10 Vpp amplitude (built-in automatic gain control)
• Up to 10 V offset (built-in offset compensation)
• Normal or inverted polarity
• 50 Ohm or 10 Kohm impedance (software-selectable)

Outputs

• Data: NRZ-L, TTL level into 50 Ohms
• Clock: TTL level into 50 Ohms
• Tape: NRZ-L/M/S, Biphase-L/M/S or RNRZ-L, TTL level into 50 Ohms

PCI Interface

• Based on PLX 9050
• 32-bit, 33 MHz interface for control/status registers
• Support for Plug & Play auto-configuration

Bit Synchronizer

• 100 bps to 10 Mbps data rate
• NRZ-L/M/S and Biphase-L/M/S PCM codes
• Loop bandwidth: 0.01% to 2% of data rate
• Tracking range: up to +/- 12% of selected bit rate

Viterbi Decoder

• Convolutional code: Rate ½, Constraint Length (K) = 7, G1 = 1111001, G2 = 1011011
• Input source: 3-bit soft symbols from Digital Costas Loop or external source
• Symbol rate of up to 10 Msymbols per second
• Coding gain of greater than 5 dB
• Programmable G1/G2 order
• Alternate symbol inversion
• Differential decoding
• Descrambling