HDRM HIGH DATA RATE MODEM OVERVIEW The HDRM is a high-rate multi-mission satellite data modem and simulation system that supports both CCSDS (for Conventional and Advanced Orbiting Systems) and TDM (Time-Division Multiplexed) formats. The HDRM performs data reception, ingest, processing, distribution and archiving functions at rates up to 1.5 Gbps. It is most commonly deployed within a satellite ground station, but is also ideal for applications including satellite integration/test and aircraft data acquisition.
SOFTWARE-DEFINED MODEM Because support for multiple missions is a core design principle of the HDRM, the system's modem is implemented as a digital software-defined radio. The radio is configurable to accommodate multiple modulation schemes, data rates, coding algorithms and data formats. It provides demodulation match filters which can be tuned to correspond to characteristics of individual transmitters, improving communication performance. The system's linear wideband front end and high dynamic range enable adaptive filtering of the received signal based on symbol rate and Doppler. These characteristics also ensure compatibility with the complex modulation and coding schemes that will be developed for future missions.
MODEM PERFORMANCE Based on Avtec's proprietary software-defined radio algorithms, the HDRM's digital receiver operates within 1dB of theoretical receive performance. The receiver's low power performance far exceeds that of conventional analog alternatives; it can reliably acquire and track signals below 0 db Es/No. An industry-leading 10 MHz of Doppler tracking bandwidth contributes to the system's multi-mission flexibility, allowing the HDRM to track signals from aircraft in addition to transmissions from low-orbit and geostationary satellites.
HIGH-SPEED FRONT-END PROCESSING The HDRM's integrated high speed front-end processor ingests the high-rate data stream output by the system's receiver, performing frame synchronization, derandomization, Low Density Parity Check (LDPC) and Turbo Product Code (TPC) Reed-Solomon error correction, CRC decoding, time tagging and network output to clients and Network Attached Storage (NAS) at rates up to 800 Mbps. The HDRM's front-end processor integrates real-time CCSDS virtual channel processing and logging capabilities at data rates to 800 Mbps, using Virtual Channel Identifier to route data to networked processing centers and network storage devices. Data files can be stored locally, or forwarded to processing centers post-pass. The system supports bulk encrypted downlink, and can be used to receive, process and then transport encrypted wideband isochronous data over IP or ATM networks. In addition to standard CCSDS service processing, it supports decryption and Rice decompression.
SIMULATION AND TEST CAPABILITIES The HDRM includes configurable simulation and file playback capability for loopback testing. It also includes a Bit Error Rate Test module for downlink and network path integrity verification.
MISSION-GRADE HARDWARE, CONFIGURATION & MANAGEMENT The HDRM is based on a telecommunications-grade CompactPCI server architecture with Core 2 Duo processors, mirrored system drives, hot-swap fans, and redundant power supplies. It provides a Gig-E Ethernet interface for monitor and control, and a Gigabit Ethernet interface for high-speed network data transfer. Storage options include direct attached RAID, FibreChannel Storage Area Network, or Network Attached Storage (NAS). The HDRM can be controlled locally or remotely via an intuitive graphical user interface, and a remote control library is provided for integration with numerous satellite mission control systems such as OS/COMET and EPOCH 2000. An SNMP agent is also available to facilitate integration with management platforms such as HP OpenView.

HDRM Specifications

Modem Specifications

• IF inputs: 2 selectable IF inputs
• IF frequency: 370 MHz, 720 MHz or 1.2 GHz
• IF bandwidth: 650 MHz, automatically adjusted based on the symbol rate
• IF impedance: 50 Ohms
• IF VSWR: 1.4:1
• Doppler tracking: up to 10 MHz
• BPSK modulation up to 400 Mbps
• QPSK modulation up to 800 Mbps
• SQPSK modulation up to 800 Mbps
• 8ary PSK up to 1.5 Gbps
• Implementation loss: < 1 dB
• Dynamic range: > 40 dB
• Signal tracking down to < 0 dB Es/No

High-Speed Front-End Processing

• Data rates up to 1.5 Gbps
• Viterbi decoding, differential decoding, frame synchronization, derandomization, LDPC, TPC, Reed- Solomon decoding and CRC decoding
• Time tagging and data quality annotation
• CCSDS virtual channel sorting with support for VCDU
• Real time disk logging and high speed network transfer

Simulation & Testing

• CCSDS and TDM data simulation at rates up to 1.5 Gbps
• Onboard 64 MB memory for high speed simulation
• Hardware synch marker, ID counter, and time stamp insertion
• CRC encoding, LDPC, TPC, Reed-Solomon encoding, randomization, and convolution coding
• Data Quality Monitoring (CCSDS and TDM) and bit/packet error rate testing
• High Speed data logging and playback
• IP High Rate Data I/O
• High-performance Gigabit Ethernet (10 GigE option) for data transfer, control & monitoring
• Real-time network data transfer (UDP, IP, multicast, TCP client/ server)
• User encapsulation formats including NASCOM RTP, IPDU, SFDU, LEO-T, EDOS
• Network protocol conversion
• Embedded SLE provider

Frame Synchronizer

• Frame sync pattern up to 64 bits
• Frame sync mask up to 64 bits
• Sync bit error threshold up to 15 bit errors
• Adaptive sync strategy with 0 to 7 check frames and 0 to 7 flywheel frames
• Bit slip window from 0 to +/-3 bits
• BPSK or QPSK automatic ambiguity resolution and correction
• Frame length up to 4096 bytes/frame
• Time tagging: 5 usec accuracy with IRIG, 10 MHz & 1 PPS input (IRIG input only, 100 usec)
• Time stamp using internal or external 10 MHz reference and 1 PPS

LDPC Decoder

• Rate 7/8, LDPC (8160, 7136)
• Error floor no higher than 10-10 BER
• Rate 1/2 AR4JA
• Supports block sizes of 1024, 4096, or 16384 bits

TPC Decoder

• Rate 7/8 TPC (128, 120)2
• 2-D TPC based on parity, hamming, and "BCH t=2" (double error correcting) code
• Constituent code size: 16, 32, 64, 128, or 256 bits
• Block size: from a few bits to 65 Kb
• Number of iterations: 2 to 16
• Reed-Solomon EC Encode/Decode
• CCSDS Reed-Solomon (RS) (255,223) error correction
• Support for interleave depth up to 16
• CCSDS Reed-Solomon (10,6) header error correction
• Shortened codeword support using "virtual fill"
• Real-time quality generation and annotation for each VCDU

CRC Error Detection Encode/Decode

• Compute frame error control field from received data using the polynomial g(x) = x^16 + x^12 + x^5 + 1
• Programmable offset from 0 to 8 bytes

Derandomizer/Pseudo-randomizer

• Exclusive OR received from data following sync pattern with pattern given by h(x) = x^8 + x^7 + x^5 + x^3 + 1
• Programmable start offset frame 0 to 8 bytes

Convolutional Encode/Viterbi Decode

• CCSDS rate=1/2, rate ¾ constraint length K=7
• Programmable G1, G2 order
• Programmable inversion of G1 and G2

Physical Specifications

• 19" rack mountable 2U (4 slot), 3U (6 slot), or 4U (8 slot) chassis offerings
• 120-220 VAC at 50 to 60 Hz power